As it is well known, in power electronic devices, in particular in power devices of the MOS type, it is important to have the possibility of operating at higher and higher frequencies while maintaining a high component reliability.
Nowadays the uses of MOS devices in fact often require the possibility of operating, both at low supply voltage (20-100V) and at high supply voltage (200-1000V), but, however, at higher and higher frequencies approaching one megahertz (MHz).
Power devices are thus subjected to very high voltage and current gradients during the transients and/or during the switchings, which may make the stresses to the device weakening the same burdensome and reduce its lifetime drastically.
As it is well known, some power MOS devices are realized by thousands or millions of elementary MOS transistors placed in parallel and individually contributing to the overall current capacity of the device.
Typically, elementary MOS transistors, as highlighted in FIG. 1, are realized on semiconductor or with polygonal cells or strips and they comprise a body region, which, in the case shown, is of the p type, formed on a suitable substrate, of the n type, and with a source region realized on top.
The body region, together with the source region, form a channel region covered by an insulating layer, for example a silicon oxide, and by a conductive layer, for example suitably doped polysilicon.
These two insulating and conductive layers represent, for each elementary MOS transistor, the gate dielectric and for the power MOS device they form a biasing mesh also called gate the mesh.
The gate mesh is connected to a terminal called gate pad and it allows the distributing of the signals inside the MOS device as well as the turning on and/or off all the elementary MOS transistors composing the power MOS device.
The gate mesh, due to the high polysilicon resistivity (>10 Ohm/[square]), exhibits resistive contributions along the path which depend on the relative position with respect to the gate pad, as highlighted in the circuit of FIG. 2. This implies that gate resistance value of each elementary transistor also depends on the distance from the gate pad.
Thus, each elementary MOS transistor, at each switch of the MOS device, responds with a time constant which, being, as known, a function of the input capacitance and of the gate resistance, will be distinct for each elementary MOS transistor.
The gate resistance is thus an important value because, together with the input capacitance of the MOS device, forms an RC circuit whose time constant is one of the most important parameters influencing the switch speed of power electronic MOS devices. These latter devices, having to operate at higher and higher frequencies, thus require a more and more reduced time constant. Consequently, manufacturers are thus trying to reduce the gate resistance, making it homogeneous for the entire MOS device so as to ensure a greater reliability in high frequency applications.
To try and solve such problem, a known technique is that of carrying out a suitable metallization of the gate, a process including creating connection buses, also called gate fingers, realized in metallic material, so as to connect the gate pad to various points of the gate mesh by “short-circuiting” them, as shown in FIG. 3 and in the corresponding circuit of FIG. 4.
A related technique is that of increasing the number of gate fingers so as to intersect the gate mesh at a greater number of points.
Although advantageous in several aspects, such a solution exhibits different drawbacks, the main one being that the presence of the gate fingers realized in metallic material reduces the active area of the power MOS device, since below the gate fingers it is often not possible to integrate the elementary MOS transistors.
Moreover, a further drawback linked to the presence of the gate fingers is due to the fact that they may limit the number and the position of the wires connecting to the source pad, thus negatively affecting the output resistance of the power MOS device.
A further known solution to reduce the gate resistance provides the decrease of the gate mesh resistance by integrating there inside a very conductive layer. Referring to FIG. 5, such a process makes use of metallic silicides, such as for example cobalt silicide (CoSi2), platinum silicide (PtSi), titanium silicide (TiSi2) or tungsten silicide (WSi2), which exhibit a layer resistivity of about one order of magnitude lower with respect to that of the unsilicided polysilicon.
For power electronic MOS devices used in faster and faster applications with low gate resistance, problems, however, emerge linked to the great voltage and current gradients during the transients.
All the solutions proposed to reduce the gate resistance exhibit the drawback that two elementary MOS transistors placed at different distances from the gate pad are “unbalanced” with respect to each other in the sense that they exhibit two different gate resistance values and thus two different switch speeds. This effect is more and more evident as faster and faster devices are realized.
FIG. 6 highlights a pattern in parallel of different elementary MOS transistors which exhibit different gate resistances according to the position wherein they are with respect to the gate pad and to the gate fingers.
The diagram in FIG. 7 shows how between elementary MOS transistors where there exists an unbalance in the resistance value, during the switch step of the MOS device, different wave forms are produced which distribute the current at stake in a non uniform way. In particular it can be verified how, the current intensity, I2, crossing the slowest component undergoes sudden increases affecting the uniformity of the overall time constant of the electronic MOS device.
Such behavior in the power MOS device is exponentially increased relative to an increase in the plurality of elementary MOS transistors. This, however, may jeopardize both the correct functionality and the operating lifetime of the MOS device itself.
For the manufacturing process used in the realization of a power electronic MOS device, it is inevitable that there are unbalances in the current flow. In fact it is good to remember that the distance between one gate finger and the other is around 200-2000 μm and in such space many elementary MOS transistors are disposed whose gate biasing occurs by means of the gate mesh. In such case the elementary MOS transistors closer to the gate fingers often will be the fastest while the others will often be slower and slower, as highlighted in FIG. 8.
Further unbalances are due to the fact that because for problems due to the assembling step it is often difficult to realize continuous and equidistant gate fingers (FIG. 9). Thus, the power MOS device obtained will exhibit areas with different distances between the gate fingers, as shown in the example of FIG. 9, and this implies the presence of a gate resistance influenced by the area with a shorter distance between the gate fingers, since in the calculation of the total resistance of these parallel resistances the areas with higher resistance will have less weight.
Moreover, it is good to reveal that although the resistivity of the material used for realizing the gate fingers is low, it is possible that the lengths of the fingers is such as to introduce resistive contributions that are significant as compared with the total gate resistance of the power electronic MOS device especially if, for lowering the metallization mesh resistance, metallic silicides are used.
As highlighted in the example of FIG. 10 and in the associated circuit of FIG. 11, the areas in correspondence with the points A and B, although being near the gate finger, exhibit a different resistance in series due to the contribution of the gate finger section AB, which could have an even higher resistance than one Ohm, with a consequent unbalance between the different areas of the power MOS device.
All these causes lead to having power electronic MOS devices weakened by the presence of areas having different gate resistances with consequent negative effects on the switching and during the extreme dynamic stresses with high values of dV/dt and/or dI/dt.
The unbalance can also cause current localizations that can cause the incorrect operation and/or the destruction of the power MOS device.
It is also known that power electronic MOS devices, especially with low voltage driving, for example those driven by means of driver with output voltage 1.8-2.5 Volt, exhibit a more and more reduced thickness of the gate oxide, typically silicon oxide. This reduction allows for threshold voltage values lower than 1 Volt without deteriorating the breakdown characteristics of the power electronic MOS device.
However, the reduction of the gate oxide thickness, together with the higher integration density, implies shallower deep junctions and shorter and shorter circuit lengths, with consequent increase of the capacitances of the elementary MOS transistors and of the total capacitance and with a slowdown of the response time during the switchings.
To try to reduce the capacitance using gate oxides other than silicon dioxide, it is known, for example, to use hafnium oxide, aluminum oxide, silicon oxide/silicon nitride multilayers and others.
Changes in the composition of the material used, however, imply drawbacks mainly linked to the necessary testing, which may require excessively long and prohibitive development times for the current market of power electronic MOS devices.
A further known technique to reduce the total capacitance of the device is that of varying the geometry of the gate oxide; such solution provides the realization of the gate oxide with two different thicknesses in active area as shown for power VDMOS devices, both with n channels and with p channels, in U.S. Pat. Nos. 6,222,232 and 6,326,271, which are incorporated by reference.
In such proposed solutions the gate dielectric exhibits two thicknesses: a thin one realized above the channel region, which allows a low threshold voltage driving, and a thicker one extended to the region of the gate/drain capacitor, which allows a significant reduction in the transient capacitance of the device and thus also the input capacitance.
The procedure to define the gate structure in the VDMOS devices, according to the prior art, mainly requires a thermal growth of a thick silicon oxide film from the underlying substrate, and a photolithographic definition in active area regions and a growth of a thin gate oxide film which will surmount the channel.
Such known technique provides the use of a photolithographic step to define the part of the thick gate electrode in the elementary MOS transistor and it provides a successive and more important photolithographic step to delineate the geometry of the gate electrode.
Considering that in the elementary MOS transistor there is the need of having a symmetrical and uniform diffused channel using a known procedure, realizing power MOS devices with double oxide thickness imposes a margin, with quite high value, between the delimitation of the gate electrode and the edge of the central thick oxide region, as it can be seen in FIG. 12.
Such margin labeled with <<1>> in FIG. 12 typically must be sufficiently wide so as to ensure that possible misalignments in the photolithographic definition of the gate electrode do not cause the extension of the channel below the thick oxide region in an asymmetrical way, on the other hand.
Obviously, the need of safeguarding the alignment of the planar structures in active area goes against the need of a greater and greater integration of power MOS transistors and thus against the need of operating with more and more reduced dimensions.
There exist realizations, obtained by using solutions as highlighted for example in the US Patent Publication No. 2002/0140042A1, which is incorporated by reference, which allow to obtain high integration density devices with self-aligned gate oxide regions. Such realizations, although advantageous under several aspects, exhibit the drawback of significantly reducing the gate mesh in thickness and width and thus they remarkably increase the gate resistance. Moreover, in such known realizations the problems for introducing a silicide layer inside the gate mesh have significantly increased.